The present invention relates to switching regulator circuits. More particularly, the present invention relates to circuits and methods for offsetting the current reduction effects caused by the use of slope compensation in switching regulator circuits.
The purpose of a voltage regulator is to provide a predetermined and substantially constant output voltage to a load from a voltage source which may be poorly-specified or fluctuating. Two types of regulators are commonly used to provide this function, a linear regulator and a switching regulator. In a typical linear regulator, the output voltage is regulated by controlling the flow of current through a pass element from the voltage source to the load.
In switching voltage regulators, however, the flow of current from the voltage source to the load is not steady, but is rather in the form of discrete current pulses. To create the discrete current pulses, switching regulators usually employ a switch (such as a power transistor) that is coupled either in series or parallel with the load. The current pulses are then converted into a steady load current with an inductive storage element.
By controlling the duty cycle of this switch (i.e., the percentage of time that the switch is ON relative to the total period of the switching cycle), the switching voltage regulator can regulate the load voltage. In current-mode switching voltage regulators (i.e., a switching regulator that is controlled by a current-derived signal in the regulator) there is an inherent instability when the duty cycle exceeds 50% (i.e., when the switch is ON for more than 50% of a given switching period). Stability is often maintained in such current-mode switching regulators by adjusting the current-derived signal used to control the regulator with a slope compensation signal.
One method of producing such a slope compensation signal is to use a portion of an oscillator signal as the compensation signal. The oscillator signal may be, for example, a ramp signal that is used to generate a clock signal that controls the switching of the regulator. The slope compensation signal can be applied by either adding the ramp signal to the current-derived signal, or by subtracting it from a control signal.
An example of a typical prior art current-mode switching regulator 100 utilizing slope compensation is shown in FIG. 1. Such a switching regulator is available from Linear Technology Corporation, Milpitas, Calif., for example, in model LT1376. Voltage regulator 100 generally comprises an output circuit 110 and a control circuit 130.
The voltage regulator of FIG. 1 operates as follows. A switch timing circuit 112 (which may be any circuit suitable for producing substantially in-phase ramp and clock signals) within control circuit 130 supplies a control signal SW ON that sets a latch 114. While latch 114 is set, it provides a signal to output circuit 110 that causes a switch 108 to turn ON and provide current from an input voltage source VIN to an output node 109. Latch 114 remains set until an output signal from a current comparator 122 causes latch 114 to reset. When reset, latch 114 turns switch 108 OFF so that current is no longer drawn from VIN. Current comparator 122 determines when to reset latch 114 by comparing a signal (IL) that is indicative of the current supplied to output circuit 110 with a current threshold value (ITH) generated by an error amplifier 124 and a slope compensation signal ISC (discussed in more detail below).
The primary purpose of output circuit 110 is to provide current pulses as directed by control circuit 130 and to convert those current pulses into a substantially constant output current. Output circuit 110 includes power switch 108 coupled to VIN (through sensing a resistor 132) and a node 107, a catch diode 102 coupled from node 107 to ground, an inductor 104 coupled from node 107 to output node 109, and a capacitor 106 coupled from output node 109 to ground. Although switching element 108 is depicted as a bipolar junction transistor (BJT) in FIGS. 1 and 3, any other suitable switching element may be used if desired.
The operation of output circuit 110 can be divided into two periods. The first is when power switch 108 is ON, and the second is when power switch 108 is OFF. During the ON period, current passes from VIN through switch 108 and flows through inductor 104 to output node 109. During this period, catch diode 102 is reverse-biased. After power switch 108 turns OFF, however, inductor 104 still has current flowing through it. The former current path from VIN through switch 108 is now open-circuited, causing the voltage at node 107 to drop such that catch diode 102 becomes forward-biased and starts to conduct. This maintains a closed current loop through the load. When power switch 108 turns ON again, the voltage at node 107 rises such that catch diode 102 becomes reverse-biased and again turns OFF.
As shown in FIG. 1, error amplifier 124 senses the output voltage of regulator 100 via a feedback signal VFB. Error amplifier 124, which is preferably a transconductance amplifier, compares VFB with a reference voltage 116 (VREF) that is also connected to amplifier 124. A control signal, VC, is generated in response to this comparison. The VC control signal is filtered by a capacitor 127 and coupled to the emitter of PNP transistor 118 and the base of NPN transistor 126. The VC signal controls transistor 126. When the value of VC is large enough to turn transistor 126 ON, a current xe2x80x9cITHxe2x80x9d flows through resistor 128. Generally speaking, the value of ITH is dependent on VC. As VC increases, so does ITH and vice versa.
The value of ITH establishes the threshold point at which current comparator 122 trips. Therefore, as ITH increases, the current threshold of switch 108 also increases to maintain a substantially constant output voltage. However, as mentioned above, current-mode voltage regulators can become unstable when the duty cycle exceeds 50%. To prevent this instability, a duty cycle proportional slope compensation signal may be subtracted from the feedback signal (ITH) to increase the rate of current rise perceived by control circuit 130. This is accomplished in FIG. 1 by applying the ramp signal from switch timing circuit 112 to a node between the emitter of transistor 126 and a resistor 125 (through a circuit generally depicted as variable current source 113). As the ramp signal progresses toward its peak, the voltage at the emitter of transistor 126 rises, impeding the flow of current, which causes the ITH to decrease. Current comparator 122 interprets this as an increase in the rate of current rise in inductor 104. This causes the perceived rate of current rise in inductor 104 to be greater than the rate of current fall, which allows regulator 100 to operate at duty cycles greater than 50% without becoming unstable.
To prevent damage to switch 108, the maximum operating current of regulator 100 is limited to a certain level by placing a voltage clamp on the VC signal. Such a voltage clamp is typically implemented as shown in FIG. 1 using a PNP transistor 118 and a fixed voltage source 120. As long as the value of VC remains within a permissible operating range, voltage source 120 keeps the emitter-base junction of transistor 118 reverse-biased so that it acts as an open circuit. However, when VC attempts to rise above a preset maximum value, transistor 118 turns ON and starts to conduct. This diverts excess current away from the VC signal so that its voltage always remains at or below the preset maximum.
One undesirable consequence of slope compensation is that the true maximum current that can pass through switch 108 decreases proportionally as the duty cycle increases. This is because as the duty cycle increases, the effective magnitude of the slope compensation signal (ISC) also increases, causing a significant drop in ITH during the latter ON portion of the duty cycle. This phenomena is of concern to circuit designers because it prevents the full current supplying capabilities of regulator 100 from being utilized at higher duty cycles.
A graphical illustration of this deficiency is generally shown in FIG. 2. In FIG. 2, the magnitude of the slope compensation signal ISC, represented by line 170, increases with duty cycle, whereas the threshold level of the voltage clamp, represented by line 180, remains constant. As can be seen, because the clamp threshold remains constant, the slope compensation signal reduces the current limit by about 30%, thus allowing only approximately 70% of the intended maximum current to pass through switch 108 when the duty cycle is at about 90%.
Although FIG. 2 shows the reduction in switch current beginning at a duty cycle of about 50%, it will be understood that the switch current will start to decrease at whatever duty cycle a slope compensation signal is added. For example, some current mode switching regulators may begin to use slope compensation at duty cycles of about 10% (or less). In this case, the current sourcing capability of the regulator will begin to drop off at duty cycles of about 10%.
One way to correct this problem is to let VC rise above the maximum level imposed by the voltage clamp when slope compensation is used. This allows ITH to remain substantially constant rather than decrease as the amount of slope compensation increases. Merely increasing the clamp voltage directly (e.g., by increasing the value of voltage source 120) is not a viable solution because the large time constant of capacitor 127 will not allow VC to respond to a changing clamp threshold fast enough. Moreover, simply adding voltage directly to VC nulls the effect of slope compensation. What is needed is a control circuit that can adjust the VC clamp threshold with respect to the slope compensation signal so that a substantially constant maximum current limit can be maintained at greater duty cycles.
It would therefore be desirable to provide a current-mode switching voltage regulator that has improved current supplying capabilities when slope compensation is used.
It would also be desirable to provide a control circuit for a current-mode switching voltage regulator that can adjust its switching threshold with respect to the magnitude of a slope compensation signal so that a substantially constant maximum current limit of the regulator may be maintained at greater duty cycles.
It would be further desirable to provide a control circuit for a current-mode switching voltage regulator that has a clamp circuit whose threshold can be adjusted with respect to the magnitude of a slope compensation signal so that a substantially constant current limit may be maintained at greater duty cycles.
It is therefore an object of the present invention to provide a current-mode switching voltage regulator that has improved current supplying capabilities when slope compensation is used.
It is another object of the present invention to provide a control circuit for a current-mode switching voltage regulator that can adjust its switching threshold with respect to the magnitude of a slope compensation signal so that a substantially constant maximum current limit of the regulator can be maintained at greater duty cycles.
It is a further an object of the present invention to provide a control circuit for a current-mode switching voltage regulator that has a clamp circuit whose threshold is adjusted with respect to the magnitude of a slope compensation signal so that a substantially constant maximum current limit may be maintained at greater duty cycles.
These and other objects of the present invention are accomplished by providing a current-mode switching voltage regulator that can maintain a substantially constant maximum current limit over a virtually full range of duty cycles. The voltage regulator includes a control circuit that has a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that the regulator can maintain a substantially constant maximum current limit at increased duty cycles.